There exist today numerous methods for monitoring the occurrence of Single Event Functional Interrupts (SEFIs) in an electronic circuit and, in particular, field programmable gate arrays (FPGAs). Since the electrical interface to an FPGA is susceptible to an SEFI, which can manifest itself as a loss of communication with the configuration memory, a periodic read back of at least one frame inside the FPGA, along with a cyclical redundancy check (CRC) calculation and comparison is performed to determine if the same configuration error persists through multiple refreshes of the configuration memory. When performing this evaluation, an assumption is made that if the same error exists through multiple refreshes of the configuration memory, the refresh is not reaching the memory and a SEFI has occurred.
Including the ability to periodically read back frames and adding CRC functionality adds complexity to the design of the configuration manager used for the electronic circuit, and an inherent delay exists in registering a SEFI since multiple refresh cycles are required as part of the evaluation process. A typical delay extends the recovery time from an event of this nature past one refresh cycle. The longer the SEFI is allowed to manifest itself, the more likely data will be corrupted within the electronic circuit.
When a SEFI detection system cannot notify the configuration manager in an electronic circuit of a SEFI within a minimal recovery time, electronic circuits are continuously operating with greater amounts of communication interference. Without a reliable and efficient SEFI detection system available, the applications for an electronic circuit of this type are limited, especially in operating environments susceptible to high amounts of radiation.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification, there exists a need in the art for improved detection of adverse events in electronic circuits.